ASIC Design Engineer

Overview

In this role you will drive architectural direction and hands-on RTL work for next-gen AI accelerators. You’ll translate concepts into production-ready hardware and collaborate with Verification, Software and Systems teams to refine designs. You’ll challenge existing approaches to improve performance, power and area while shaping the product’s technical direction. This is a fast-paced, ownership-driven environment where your work directly impacts silicon strategy and compute efficiency.

Responsibilities

• Design and implement high-performance RTL for AI accelerator architectures
• Contribute to architectural definition and future product roadmaps
• Optimize RTL for performance, power and silicon area
• Evaluate architectural trade-offs and propose design improvements
• Collaborate with Verification, Software and Systems Engineering teams
• Define and document micro-architectures, interfaces and design specifications
• Support integration into complex SoC environments

Key requirements

• Strong RTL design experience using Verilog or SystemVerilog
• Experience delivering ASIC designs through to silicon
• Exposure to FPGA development and prototyping
• Experience implementing high-performance digital or signal-processing hardware
• Knowledge of integrating accelerator IP into Arm or RISC-V based SoCs
• Scripting experience using Python, Tcl or similar
• Understanding of AI workloads or hardware acceleration concepts
• Experience using Git and modern development workflows
• Familiarity with simulation and verification environments
• team collaboration
• technical ownership
• ability to tackle unfamiliar challenges
• Verilog/SystemVerilog RTL
• ASIC design flow to silicon
• FPGA prototyping

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