Digital Electronics Principal Verification Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise.

Increase your chances of an interview by reading the following overview of this role before making an application. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.

Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Digital Electronics Principal Verification EngineerLocation: EdinburghReports to: Design Engineering Group DirectorJob Overview: The Cadence Silicon Solutions Group (SSG) develop leading edge Intellectual Property (IP) for a variety of High-Tech Markets.

The Cadence IP solutions allow our Customers to tackle IP-to-SoC development in a system context, enabling them to focus on product differentiation and to reduce time to volume. The Cadence SSG Vision is to deliver industry leading IP and Chiplet solutions to enable our customers to be successful across these fast-moving application spaces.

The Digital Principal Verification Engineer will be based in Edinburgh, Scotland as part of an experienced Chiplet Team with long established research and development sites in Europe and India. Job

Responsibilities

Development of Verification and Emulation Environments for complex Chiplet DesignsDevelopment of UVM-SV Scoreboards for self-checking regressionsDevelopment of Functional Coverage as part of Metric Driven Verification EnvironmentsDevelopment of SystemVerilog Assertions for use in Formal and Simulation EnvironmentsDevelopment of Emulation Environments based on Cadences Palladium Emulator ProductIntegration of Cadence Verification IP (VIP) for Simulation EnvironmentsIntegration of Accelerated VIP (AVIP) for Emulation EnvironmentsDefinition and Management of Verification Plans (vPlans) using Cadence vManager toolsCreation and Management of Automated Regression Environments, e.g.

Jenkins, GITParticipation in Technical Review Meetings and Checklist Reviews as part of ISO-9001 Close Collaboration with Architects and Design Engineers to debug complex test scenariosJob

Qualifications

Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline10+ years' experience in microelectronics/EDA industryExperience of Verilog RTL Design essential Experience of Metric Driven Verification (MDV) essentialExperience of Formal Verification Methodologies essentialExcellent oral and written English essentialSelf-motivated with excellent planning, interpersonal, and communication skillsAdditional Skills/Preferences: Experience of Front-end design tools covering LINT, Synthesis, CDC Analysis preferredExperience of Quality processes, such as ISO-9001 & ISO-26262 preferredAdditional Information: Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization.

We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace. We're doing work that matters. Help us solve what others can't.SummaryLocation: EDINBURGH 01Type: Full time

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