FPGA Verification & Control Systems Engineer

At Zero Point Motion, the FPGA is not glue logic.

It is a core part of the sensing system.

This role exists to design, verify, and operate real-time digital systems that directly interact with physical reality: MEMS motion, photonic signals, noise, timing, and control loops.

If you think of FPGA work as abstract RTL design, this role is not for you.

If you think of digital systems as applied mathematics implemented in silicon, it might be.

The Role

As an FPGA / Digital Systems Engineer, you own real-time digital control and signal processing that directly interfaces with MEMS and photonic hardware.

Your work directly determines lock stability, noise floors, measurement fidelity, and whether demos succeed or fail.

This is a hands-on role. Verification quality, timing discipline, and physical intuition matter more than clever architectures. If you write the code, you own proving that it is correct.

The role sits close to R&D: the FPGA is part of discovering system truth, not just implementing a frozen design.

What You’ll Do

Digital control & signal processing

Design, implement, and verify FPGA systems interfacing with photonic sensors, MEMS devices, and high-speed ADCs/DACs

Implement and stabilise real-time systems such as:

PLLs

AGC

nested feedback loops

quadrature demodulation

force-to-rebalance control

Reason explicitly about timing, latency, jitter, phase noise, quantisation, and numerical stability

Digital ↔ physical reasoning

Translate mathematical models and control theory into discrete-time digital implementations

Understand how RTL decisions affect mechanical motion, optical phase, thermal drift, and noise coupling

Treat the FPGA as part of the physical system, not an isolated digital block

Hardware interfaces & IO

Implement and debug SPI, I²C, UART, GPIO, and high-speed ADC/DAC interfaces

Design safe clock-domain crossings intentionally

Build reliable data logging and streaming under real-time constraints

Verification & observability (non-negotiable)

Build proper verification environments:

structured testbenches

assertions tied to invariants

deterministic stimuli

quantitative pass/fail metrics

Verification must be automated, repeatable, and explainable

Eyeballing oscilloscope traces is not verification

Design for observability with internal instrumentation and clear failure modes

Tooling, lab work & data

Write clean, disciplined RTL (Verilog / SystemVerilog)

Use Python as a first-class tool for test automation, bring-up, verification support, and data analysis

Be fluent with lab instrumentation and understand their limitations, not just their outputs

Required Background

You must have:

At least 3 years of relevant FPGA, digital design, or control systems experience. If you have less than 3 years’ experience, please apply to ZPM Launchpad by clicking here instead.

Strong fundamentals in digital design and real-time systems

Solid grounding in control theory or signal processing

Hands-on experience bringing up FPGA designs on real hardware

Experience implementing and verifying control loops, PLLs, or equivalent feedback systems

Comfort working at the boundary between digital logic, analog signals, and physical systems

High personal standards around correctness, verification, and documentation

Experience with ASIC flows is a plus, not a requirement

Who This Role Is For

This role is not for:

MATLAB-first engineers

simulation-only designers

FPGA developers who avoid lab work

people who “verify” by visual inspection

engineers uncomfortable with noise, timing, or pressure

What This Role Is Not

This is not:

a pure web, SaaS, or framework-driven role

a narrowly scoped backend position

a job for people who only write one-off scripts and move on

a place for over-abstracted code no one can debug

a role for people who wait for perfect specifications

How You Show Up

You are motivated by the underlying mathematics, not just by making something work

You do not ship what you cannot explain

You treat verification as a core engineering discipline

You communicate clearly, especially under pressure

You design margins so systems work without heroics

What Success Looks Like

After 6–12 months:

FPGA-based control loops are stable, low-noise, and explainable

Verification is trusted because it is systematic and repeatable

Timing closure is boring because it was designed correctly

Demos work because margins exist, not because of last-minute tuning

Bugs are found early and are diagnosable when they do occur

The FPGA is a transparent, instrumented part of the system - not a black box

Working with us

Compensation: Our framework is built on fairness and transparency, with regular reviews to reflect growth and performance.

Benefits: Share options, pension, and private medical insurance.

Culture: A deep-tech rocketship backed by leading investors. We’re building breakthrough technology with real commercial impact. Pace is high. Standards are higher.

Zero Point Motion is determined to foster belonging and empowerment at work. We are committed to providing a work environment where there’s a zero-tolerance approach to discrimination, and everyone is treated with respect. Equity, diversity and inclusion are central to our mission, and we strongly encourage candidates of all different backgrounds and identities to apply. If you need assistance or an accommodation due to a disability, please contact us.

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