Senior CPU Design Verification Engineer

Overview

In this role you contribute to the verification of digital CPU designs within a high‑scale AI/hardware platform. You’ll build and refine verification components and constrained-random testbenches, driving coverage closure and sign‑off toward tape-out. You collaborate with design and verification engineers to model corner cases and ensure functionally correct blocks. The role sits in a cross‑functional R&D team focused on cutting‑edge silicon and infrastructure capabilities. You’ll work on scalable verification strategies that support industry‑leading performance and reliability.

Responsibilities

• Plan verification strategies by understanding design specs and engaging with design engineers
• Create and enhance constrained‑random verification environments using SystemVerilog and UVM, and use SVA/formal tools
• Define and measure coverage, including corner cases
• Debug verification tests with design engineers to ensure correct functionality
• Close coverage gaps and progress toward tape‑out

Key requirements

• Bachelor’s degree in electrical engineering or equivalent practical experience
• 8 years of experience in verification components and environments using standard methodologies
• Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs
• collaboration
• problem solving
• driven by quality
• SystemVerilog
• UVM
• SVA

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