Staff Formal Verification Engineer (GPU)

Overview

As Lead GPU Formal Verification Engineer, you drive the strategy and execution of AMD’s formal verification for the next generation graphics IP. You will shape the roadmap, methodology, and infrastructure in collaboration with architecture, design, and central verification teams.

You lead a team to scale verification across complex datapath and control logic, tackling challenging convergence with advanced techniques. You will mentor engineers and promote adoption of formal verification throughout the IP development lifecycle.

This role blends leadership, cutting-edge verification, and cross‑functional impact to advance AMD’s graphics solutions.

Responsibilities

• Define long-term formal verification strategy and technical roadmap
• Develop and extend verification methodology for full graphics design ( datapath and control )
• Scale verification for large, critical designs to achieve high quality
• Broaden adoption of formal verification across the IP development lifecycle
• Resolve convergence challenges using techniques like induction, reduction, abstraction
• Define and drive best-in-class verification infrastructure to boost productivity
• Enable more verification engineers to use advanced verification technologies
• Lead research in emerging formal verification domains (security, safety, low power, architect level)
• Explore formalization of ISA and memory models for GFXIP
• Stay updated on trends in formal verification and build relationships within AMD
• Foster cross-department innovation and collaboration

Key requirements

• In-depth knowledge of formal verification algorithms, engines and use cases
• Proven expertise in SystemVerilog assertion and abstract model development
• Experience with formal verification tools (JasperGold, VC Formal, Murphi, theorem prover)
• Track record delivering high-quality verification under tight schedules for large-scale processors
• Strong understanding of computer architecture and graphics pipeline
• Experience developing formal verification infrastructure for FPV, DPV, SEV and related use cases (preferred)
• effective communicator
• leadership and influence
• cross-team collaboration
• formal verification algorithms
• SystemVerilog assertions
• abstract modeling

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