Staff Verification Engineer

Overview

In this role you will verify sub-system integration, IO behavior, and performance for PCIe and CXL within Arm-based SoCs. You’ll collaborate with architects, RTL and verification teams across multiple regions to shape a scalable verification strategy and test infrastructure. You will craft test plans, build SystemVerilog/Verilog/UVM environments, and debug issues to ensure robust, high-performance IO subsystems. This is a unique opportunity to impact next-generation silicon on cutting-edge process nodes and packaging, contributing to Arm’s premium IP ecosystem.

Pay / Benefits

• hybrid working
• accommodations during recruitment
• diverse and equal opportunity employer

Responsibilities

• Craft test plans for sub-system IO verification and performance analysis
• Develop SystemVerilog/Verilog/UVM testbenches and tests; debug failures
• Verify PCIe/CXL integration at sub-system level, including SMMU and GIC interop
• Collaborate with design/microarchitecture teams on verification methodology and system performance
• Improve verification methodologies and processes
• Mentor and guide junior team members; coordinate with PM on plans and schedules

Key requirements

• 5+ years in verification of PCIe or CXL subsystems/SoCs
• Strong Verilog HDL and digital hardware design knowledge
• Experience in PCIe, CXL and IDE feature verification and performance analysis
• Knowledge of System Memory Management Unit and Generic Interrupt Controller integration with PCIe
• Experience with PCIe & CXL IPs and emulation-friendly transactors
• Experience on simulation and emulation platforms
• Proficiency in UVM-based verification
• Knowledge of verification strategies: test plans, coverage, verification sign-off, formal methodology
• Collaboration and cross-functional teamwork
• Strong debugging and problem-solving mindset
• Clear communication and documentation
• Verilog/SystemVerilog
• UVM based verification
• PCIe verification

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