Verification / Senior Verification Engineer

Overview

In this role you will own verification across the full stack to ensure high quality, reliable systems. You will work closely with designers and architects to shape verification plans and test strategies. You’ll develop scalable testbenches and self-testing methods to validate complex hardware and embedded software. You’ll maintain the verification environment and track regressions and coverage to meet Riverlane’s standards. This is a chance to contribute to cutting-edge quantum technology and learn the quantum domain along the way.

Pay / Benefits

• annual bonus plan
• private medical insurance
• life insurance
• contributory pension scheme
• equity
• 28 days annual leave plus bank holidays and enhanced family leave

Responsibilities

• Define verification plans with designers and architects based on design specs
• Own test strategies across block-level and system-level designs
• Develop and implement scalable testbenches, checkers, reference models and coverage groups in SystemVerilog
• Implement self-testing, directed and random tests to validate system performance
• Maintain the verification environment, track regressions, coverage metrics and bugs to ensure quality and reliability

Key requirements

• Demonstrable commercial experience in functional verification with ownership of verification planning and strategy
• Proven testbench design experience with UVM/OVM
• Knowledge of SystemVerilog assertion (SVA)
• Exposure to C, C++ and Python
• Proactive, independent work style and strong collaboration and communication
• Ability to work with ambiguity and changing requirements
• Experience debugging across RTL, simulation and hardware
• Nice to have: formal verification experience
• collaboration
• excellent communication
• proactive
• SystemVerilog
• UVM/OVM
• SystemVerilog assertion (SVA)

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